This is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Two J-K Master/Slave Flip Flops in a 14-Pin DIP Package
Outputs Directly Interface to CMOS, NMOS and TTL
Large Operating Voltage Range
Wide Operating Conditions
74LS73
http://www.futurlec.com/74/IC7473.shtml
Two J-K Master/Slave Flip Flops in a 14-Pin DIP Package
Outputs Directly Interface to CMOS, NMOS and TTL
Large Operating Voltage Range
Wide Operating Conditions
74LS73
http://www.futurlec.com/74/IC7473.shtml
